Logo image
返回
Fabrication of CFETs with Vertically Stacked p-SiGe/n-Si Channels by SiGe/Ge/Si Multilayer Epitaxy and Ge Selective Etching
期刊文章

Fabrication of CFETs with Vertically Stacked p-SiGe/n-Si Channels by SiGe/Ge/Si Multilayer Epitaxy and Ge Selective Etching

C.-L. Chu, S.-H. Chen, W.-Y. Chang, S.-H. Hsu, G.-L. Luo 和 W.-F. Wu
ACS Applied Electronic Materials, 卷.6(6), 頁碼.4304-4310
2024
DOI: https://doi.org/10.1021/acsaelm.4c00411
Web of Science ID: WOS:001237253800001

摘要

complementary FET (CFET) multilayer epitaxy Nanosheet FET selective etching SiGe/Ge/Si multilayer structure straightforward S/D implantation Etching Fabrication Germanium Low-k dielectric Multilayers Si-Ge alloys Silica Silicon Complementary FET Ge/Si multilayer Inversion modes Multilayer epitaxy Multilayer structures Nanosheet FET Process flows Selective etching Sige/ge/si multilayer structure Straightforward S/D implantation Nanosheets
This study presents a straightforward approach for fabricating heterogeneous complementary FET (CFET) devices. The process flow commences with a SiGe/Ge/Si epitaxial multilayer structure grown on a SOI substrate. The source/drains for both stacked devices were straightforwardly performed through P and B implantations with precise depth control, respectively. The isolation of the top p-SiGe FET from the bottom n-Si FET was achieved by etching away the middle Ge sacrificial layer and subsequently filled with SiO2 dielectric material. The etching selectivity of Ge over Si and Si0.8Ge0.2 by utilizing a H2O2 solution was nearly infinite, resulting in a flawless structure with p-SiGe channels stacked over n-Si channels. Finally, a functional CFET inverter device composed of a top inversion mode (IM) SiGe nanosheet pFET and a bottom IM Si nanosheet nFET was demonstrated. © 2024 American Chemical Society.

檔案與連結 (1)

url
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85194928420&doi=10.1021%2facsaelm.4c00411&partnerID=40&md5=1e107580eae372700a0e6fe65e45c093檢視

相關連結

指標

1 檢視次數

詳細資料

Logo image