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Fabrication of p-SiGe/n-Si NSs CFET Using Single-Step Ge-Selective Etching Method and Wafer-Bonding Technique
期刊文章

Fabrication of p-SiGe/n-Si NSs CFET Using Single-Step Ge-Selective Etching Method and Wafer-Bonding Technique

C.-L. Chu, S.-H. Chen, S.-H. Hsu, G.-L. Luo 和 W.-F. Wu
IEEE Electron Device Letters, 卷.46(9), 頁碼.1644-1647
2025
DOI: https://doi.org/10.1109/LED.2025.3587731
Web of Science ID: WOS:001565172600029

摘要

complementary FET (CFET) multilayer epitaxy Nanosheet FET selective etching SiGe/Ge/Si multilayer structure Etching Germanium compounds Lithography Multilayers Nanosheets Silicon compounds Silicon wafers Wafer bonding Complementary FET Multilayer epitaxy Multilayer structures Nanosheet FET Selective etching Selectively etchings Si layer SiGe layers Sige/gelsi multilayer structure Single-step Fabrication
The fabrication of heterogeneous p-SiGe/n-Si channel CFETs presents significant challenges. In a single fin structure, selectively etching the Si layer while preserving the SiGe layer for the p-FET and selectively etching the SiGe layer while preserving the Si layer for the n-FET requires two opposite etching steps. This process becomes particularly complex because of the additional local lithography required. In this study, CFETs with multiply stacked p-SiGe/n-Si nanosheet channels by using Ge interlayers as sacrificial layers are demonstrated based on the wafer-bonding process flow. © 1980-2012 IEEE.

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