摘要
For current semiconductor technology, interfacial crack in stacked thin films of Cu/low-k damascene integration is a critical reliability issue that needs to be urgently resolved. In addition to the measurement of 4-point bending test, how to precisely estimate the adhesion energy between dissimilar films through simulation, based on fracture mechanics is important while designing robust interconnect structures as well as developing nextgeneration low-k materials. Distinct from the former studies, this research proposes a novel tie-release crack prediction technique based on finite element calculations in order to consider the stress-induced impacts on the thermomechanical reliability of the microelectronic package with a low-k chip during the different cracking length of film interfaces. To ensure the correctness and feasibility of the presented technique, a plastic ball array (PBGA) package with stacked Cu/low-k interconnects is implemented as test vehicle to validate actual testing data of experiments and evaluate the variation of interfacial cracking energy while silicon chip becomes thinner. Through the combination of J-integral approach with the technique of global-local submodeling, all the predicted results for the forgoing referred cases reveal a good agreement with the physical behaviors of devices. Therefore, it can be concluded that the proposed methodology is highly reliable in estimating the occurrence opportunities of interfacial crack. © Springer Science+Business Media, LLC 2009.