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Ge1 - XSix on Ge-based n-type metal-oxide semiconductor field-effect transistors by device simulation combined with high-order stress-piezoresistive relationships
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Ge1 - XSix on Ge-based n-type metal-oxide semiconductor field-effect transistors by device simulation combined with high-order stress-piezoresistive relationships

Chang-Chun Lee, Chia-Ping Hsieh, Pei-Chen Huang, Sen-Wen ChengMing-Han Liao
Thin Solid Films, 卷.602, 頁碼.78-83
03/2016

摘要

Mobility gain n-Type metal-oxide-semiconductor field effect transistor Simulation Strained germanium silicon Stress Tensile contact etching stop layer Electronic Optical and Magnetic Materials Surfaces and Interfaces Surfaces Coatings and Films Metals and Alloys Materials Chemistry
The considerably high carrier mobility of Ge makes Ge-based channels a promising candidate for enhancing the performance of next-generation devices. The n-type metal-oxide semiconductor field-effect transistor (nMOSFET) is fabricated by introducing the epitaxial growth of high-quality Ge-rich Ge <sub>1 - x</sub> Si <sub>x</sub> alloys in source/drain (S/D) regions. However, the short channel effect is rarely considered in the performance analysis of Ge-based devices. In this study, the gate-width dependence of a 20 nm Ge-based nMOSFET on electron mobility is investigated. This investigation uses simulated fabrication procedures combined with the relationship of the interaction between stress components and piezoresistive coefficients at high-order terms. Ge <sub>1 - x</sub> Si <sub>x</sub> alloys, namely, Ge <sub>0.96</sub> Si <sub>0.04</sub> , Ge <sub>0.93</sub> Si <sub>0.07</sub> , and Ge <sub>0.86</sub> Si <sub>0.14</sub> , are individually tested and embedded into the S/D region of the proposed device layout and are used in the model of stress estimation. Moreover, a 1.0 GPa tensile contact etching stop layer (CESL) is induced to explore the effect of bi-axial stress on device geometry and subsequent mobility variation. Gate widths ranging from 30 nm to 4 μm are examined. Results show a significant change in stress when the width is <300 nm. This phenomenon becomes notable when the Si in the Ge <sub>1 - x</sub> Si <sub>x</sub> alloy is increased. The stress contours of the Ge channel confirm the high stress components induced by the Ge <sub>0.86</sub> Si <sub>0.14</sub> stressor within the device channel. Furthermore, the stresses (S <sub>yy</sub> ) of the channel in the transverse direction become tensile when CESL is introduced. Furthermore, when pure S/D Ge <sub>1 - x</sub> Si <sub>x</sub> alloys are used, a maximum mobility gain of 28.6% occurs with an ∼ 70 nm gate width. A 58.4% increase in mobility gain is obtained when a 1.0 GPa CESL is loaded. However, results indicate that gate width is extended to 200 nm at this point.

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