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General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects
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General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects

Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans TsaiWu-Tung Cheng
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 卷.34(11), 頁碼.1836-1846
11/2015

摘要

2.5-D Stacked IC Built-In Self-Repair Built-In Self-Test Interposer Post-bond Test Pulse-Vanishing Test Timing Fault Software Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering
A faulty interposer in a 2.5-D integrated circuit often results in a hefty loss as the potentially expensive known-good-dies bonded on the interposer will have to be discarded as well. To avoid such a last-minute loss during a multichip integration process, built-in self-repair (BISR) is highly valuable. Even though there have been many BISR schemes in the literature, the proposed method offers a number of distinct features. First, it can target not only catastrophic faults, but also timing faults. Second, it can be applied to general multi-pin interconnects and it can be applied to repair an interposer with multiple faulty interconnects. Third, it can perform the test-and-then-repair flow on-the-fly, and thereby eliminating the overhead of extra repair storage incurred in previous methods.

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