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Hardware-efficient systolic architecture for inversion and division in GF(2m)
Journal article   Peer reviewed

Hardware-efficient systolic architecture for inversion and division in GF(2m)

J.-H. Guo and C.-L. Wang
IEE Proceedings: Computers and Digital Techniques, Vol.145(4), pp.272-278
1998

Abstract

Finite field division Finite fields inversion Parallel-in parallel-out architecture Standard basis Systolic array VLSI
Two parallel-in parallel-out systolic arrays for computing inverses and divisions in finite fields GF(2 m ) with the standard basis representation are presented. Both architectures realise a new variant of Euclid's algorithm. One of the proposed arrays involves O(m 2 ) area complexity and O(1) time complexity, while the other involves O(m) area complexity and O(m) time complexity. They are highly regular, modular and thus well suited to VLSI implementation. Compared to existing related systolic architectures with the same time complexity, our proposed arrays involve less chip area and smaller latency. It should be noted that, to perform inversion only, both the proposed arrays can be simplified. © IEE, 1998.

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