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High-Performance Stacked Double-Layer N-channel Poly-Si Nanosheet Multigate Thin-Film Transistors
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High-Performance Stacked Double-Layer N-channel Poly-Si Nanosheet Multigate Thin-Film Transistors

Lun-Chun Chen, Yu-Ru Lin, Yu-Shuo ChangYung-Chun Wu
IEEE Electron Device Letters
07/2017

摘要

Active matrix liquid crystal displays Active matrix organic light emitting diodes and three-dimensional (3D) Crystallization Logic gates nanosheet (NS) Resistance Thin film transistors thin-film transistor (TFT) Three-dimensional displays Electronic Optical and Magnetic Materials Electrical and Electronic Engineering
A high-performance stacked double-layer N-channel poly-Si nanosheet (NS) multigate thin-film transistor (DLNS-TFT) is demonstrated successfully. The proposed device has low cost, is easy to fabricate, and is compatible with Si MOSFET, AMOLED, and AMLCD fabrication. This DLNS-TFT reveals high driving current (&null A/um), high I on / Ioff ratio (&null), high mobility (42 cm2 /Vs), and low parasitic resistance, when compared with single-layer nanosheet TFT (SLNS-TFT). The DLNS-TFT also has a high density and satisfies the driving current monolithic multilayer 3D (M3D) IC in the ITRS 2015 version technology roadmap to the year 2030.

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