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Hybrid P-Channel/N-Substrate Poly-Si Nanosheet Junctionless Field-Effect Transistors with Trench and Gate-All-Around Structure
期刊文章

Hybrid P-Channel/N-Substrate Poly-Si Nanosheet Junctionless Field-Effect Transistors with Trench and Gate-All-Around Structure

Yu-Ru Lin, Che-Hsiang Cheng, Yi-Ruei Jhan, Erry Dwi Kurniawan, Yan-Ting Du, Yu-Hsien LinYung-Chun Wu
IEEE Transactions on Nanotechnology, 卷.17(5), 頁碼.1014-1019
09/2018

摘要

gate-all-around (GAA) Junctionless field-effect transistor (JLFET) nanosheet (NS) raised source and drain trench Computer Science Applications Electrical and Electronic Engineering
This paper demonstrates the gate-all-around P/N hybrid nanosheet p-channel junctionless field-effect transistors (GAA NS-JLFET) with trench and raised source and drain structure. The GAA NS-JLFET exhibits the superior electrical properties, including high field-effect mobility (18.9 cm <sup>2</sup> /Vs), high on/off current ratio (>5 × 10 <sup>6</sup> ), steep subthreshold slope (136 mV/dec.), and low DILB (60 mV/V). The high mobility and steep subthreshold slope of this GAA NS-JLFET indicates that the conducting hole filled the whole thin nanosheet channel. This GAA NS-JLFET is simple to fabricate and highly favorable for use in advanced system-on-panel and three-dimensional stacked ICs applications.

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