摘要
Multi-scale modeling construction and subsequent stress analysis for the mechanical reliability estimation of three-dimensional (3D) integrated circuit (IC) packages is challenging. This paper presents a simulation-based methodology to calculate the equivalent mechanical properties of 3D-ICs through-silicon via (TSV) interposer composed of silicon chip and copper (Cu)-filled metal to resolve this difficulty. The obtained material properties can be utilized in non-concerned regions of analytic structure to reduce modeling complexity significantly and preserve the predicted accuracy in critical locations of 3D-IC packaging simultaneously. The verification of the corresponding analytical solutions ascertains the high reliability of the results predicted by the proposed approach. The results indicate that TSV pitch is a key design factor that dominates the characteristic of a silicon interposer with array-type Cu-filled TSV. The effect resulting from TSV can be ignored as the pitch exceeds 40 lm, and pure silicon interposer is assumed to exhibit an isotropic behavior in the related stress assessment using finite element analysis. © 2012 Elsevier B.V. All rights reserved.