摘要
Microwave annealing with subsequent rapid thermal annealing (MWA+RTA) is proposed for HfZrO<sub>x</sub>-based germanium (Ge) p-channel ferroelectric FET (p-FeFET) memory to concurrently improve the interfacial quality while obtaining the required polarization, leading to a memory window of 2.5 V by &null V operation, good read latency, robust endurance up to 10 <sup>7</sup> cycles for 1 bit/cell operation and each stable state for 3 bits/cell (triple-level cell, TLC) operation up to 10 <sup>5</sup> cycles for the first time. Reversing the annealing sequence (RTA+MWA) degrades the performance and attests to the importance of thermal budget control. The proposed annealing scheme makes the Ge FeFETs, even with planar structure, quite competitive compared to other Si-, SiGe- and Ge-based FeFETs in terms of low-voltage TLC capability with high reliability, enabling high-density embedded memory for future nodes.