Logo image
Improved erasing speed in junctionless flash memory device by HfO 2Si3N4 stacked trapping layer
Journal article   Peer reviewed

Improved erasing speed in junctionless flash memory device by HfO 2Si3N4 stacked trapping layer

Chun-Yuan Chen, Kuei-Shu Chang-Liao, Kuen-Te Wu and Tien-Ko Wang
IEEE Electron Device Letters, Vol.34(8), pp.993-995
2013

Abstract

Charge-trapping flash memory HfO2 high- junctionless poly-Si Si3N4
A junctionless (JL) polycrystalline-based flash memory device with HfO 2 Si 3 N 4 (HN}) stacked trapping layer is studied for the first time. Effects of the HN stacked trapping layer on JL and inversion-mode (IM) flash devices are compared. JL device shows faster programming speed than the IM one because of its heavily doped n-channel. Specially, comparable erasing speed of JL device can be achieved by HN stacked trapping layer due to more effective electron detrapping. JL device with HN stacked trapping layer also shows better retention characteristics and keeps a larger window after 10 5 programming/erasing cycles, which makes it promising for 3-D memory integration in the future. © 1980-2012 IEEE.

Metrics

1 Record Views

Details

Logo image