摘要
Prior to contact silicide formation, cryogenic Ge pre-amorphization implantation (PAI) was adopted in sub-20 nm FinFETs to investigate how device characteristics can be affected. As compared to room-temperature PAI, cryogenic PAI does not enhance drive current from the viewpoint of mean value, however, it significantly improves variation in device parameters such as sub-V t swing (SS), drain induced barrier lowering (DIBL) and total series resistance (R Total ) for N-FinFETs by 22%–34% which is due to a reduced number of end of range (EOR) defects caused by Ge PAI. However, the benefit is not observed for P-FinFETs since its source/drain is composed of SiGe which is intrinsically less prone to form EOR defects. In addition, cryogenic PAI also contributes to leakage current reduction for N-FinFETs including gate induced drain leakage (GIDL) by 67%, sub-V t leakage by 50% and junction leakage by 67% which is primarily due to a lower number of EOR defects that make fewer native point defects. The mechanism for pronounced GIDL reduction for I/O devices than core devices is also proposed. Besides the improved device uniformity as well as leakage current, the process can be fully integrated into incumbent VLSI technology and holds great potential for sub-10 nm node.