摘要
This letter concerns the electrical properties of floating gate (FG) that has undergone top nitridation, used in NAND flash memory devices As the dimensions are scaled down to 5 nm and beyond, the use of a thinner inter-poly dielectric (IPD) can provide the required gate coupling ratio, leaving more room for the control gate poly filling between the FG. However, the effect of the IPD scaling on data retention capability is the main bottleneck. Two interesting retention failure phenomena are demonstrated in a sample of thin bottom poly oxide (BPO). They are attributed to the enhanced degradation of the electrical field at the top corners of the FG and the potential difference between neighboring FG along the WL direction. These phenomena must be taken into consideration while setting the limits of the BPO in the IPD film scheme. The proposed FG top nitridation overcomes this limitation on the thinning of the bottom oxide improving the data retention characteristics of NAND flash memory devices. © 2014 IEEE.