摘要
Voids with stress migration (SM) failure mode can occur in a Cu trench with a continuous interconnect scaling down to several nanometers. The increase in SM driving force during the process flow of Cu/low-k or Cu/extra low-k dual damascene is estimated with finite element analysis combined with the process-oriented modeling technique. The critical trench width reductions at different nodal technologies of nano devices and their effects on the SM driving force are analyzed. Moreover, several failure factors and mechanisms in barriers and metal caps are investigated to decrease large stress gradients in Cu trenches with narrow widths. The metal cap scheme composed of a CoWP layer is suggested. Another proposed approach is to decrease the deposition process temperature of the SiCN dielectric cap. The predicted simulation results are regarded as guidelines to enhance the long-term reliability of highly scaled interconnects in advanced back-end-of-line technologies.