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Improving memory traffic by assembly-level exploitation of reuses for vector registers
Journal article   Peer reviewed

Improving memory traffic by assembly-level exploitation of reuses for vector registers

Chih-Yung Chang, Tzung-Shi Chen and Jang-Ping Sheu
Journal of Supercomputing, Vol.17(2), pp.187-204
09/2000

Abstract

In this paper, we propose a compilation scheme to analyze and exploit the implicit reuses of vector register data. According to the reuse analysis, we present a translation strategy that translates the vectorized loops into assembly vector codes with exploitation of vector reuses. Experimental results show that our compilation technique can improve the execution time and traffic between shared memory and vector registers. Techniques discussed here are simple, systematic, and easy to be implemented in the conventional vector compilers or translators to enhance the data locality of vector registers.

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