Abstract
We have successfully employed scanning capacitance microscopy (SCM) operated under low photoperturbation to investigate electrical junction profiles in low-energy BF 2 + -implanted silicon wafers treated by various annealing sequences. Differential capacitance images reveal that rapid thermal annealing (RTA) followed by furnace annealing (FA) treatments (RTA + FA) can result in a narrower junction width and a shallower electrical junction depth than FA followed by RTA treatments (FA + RTA). Experimental results also indicate that the wider junction of the FA + RTA treated sample is due to the shallower concentrated distribution of electrically activated boron atoms upon annealing. Subtle correlations between electrical junctions and annealing conditions are discussed. © 2004 The Electrochemical Society. All rights reserved.