摘要
Impact of SiO2 capping layer on the quality of poly-GeSn film and characteristics of bottom-gate junctionless (JL) p-channel thin films transistors (P-TFTs) were studied. From the analysis results of X-ray diffraction (XRD) and Hall-effect measurement, the amorphous GeSn film starts to crystallize at 450 degrees C while the crystallinity enhances at 500 degrees C by employing rapid thermal annealing (RTA) as the film crystallization process. With capping layer on the whole region, the hole concentration becomes too high to turn the JL P-TFTs off. However, by limiting capping layer on source/drain region to increase hole concentration, total series resistance is reduced due to lower sheet resistance and contact resistance, which consequently improves the drive current, I-ON/I-OFF ratio and field-effect mobility. Based on the best process conditions and structure to form the poly-GeSn JL P-TFTs, I-ON/I-OFF ratio up to 5.6 x 10(2) are achieved while peak field-effect mobility of 20.8 cm(2)/Vs is obtained. Moreover, the low thermal budget process of 500 degrees C for 30 sec enables next-generation monolithic 3D-ICs. (C) 2019 The Electrochemical Society.