Abstract
In this paper, a physical mechanism is proposed where the holding voltage of the semiconductor-controlled rectifier (SCR) is predominated by the accumulation of minority carriers. Two-dimensional simulation is used to demonstrate this mechanism where the carrier distribution of SCR devices is calculated and analyzed. It has been clearly proven that the distribution of minority carriers highly correlates to holding voltage. Accordingly, a layout approach has also been designed and experiments have confirmed that an increment in holding voltage can be performed. It can be concluded that the optimization of the topological structure will markedly increase holding voltage and eventually prevent the complementary metal-oxide-semiconductor (CMOS) integration circuit from minimizing the latch-up effect. Moreover, because of its high current capabilities, the optimized SCR can be used as an ideal candidate for electrostatic discharge protection (ESD) applications. © 2009 The Japan Society of Applied Physics.