Abstract
Extrusions on W-polycide (WSi x ) gate sidewalls, sheet resistance {R s ), and device characteristics as well as memory cell performance for 70 nm NAND flash memory cells are investigated. To prevent the formation of unstable W-Si-O compounds, oxidation of WSi x gate sidewalls prior to oxygen plasma ashing for source/drain photo resist removal is implemented, and then WSi x extrusion can be absolutely suppressed. Moreover, the sheet resistance of a WSi x gate can be improved near 40% by additional sidewall oxidation due to enlarged grain size and reduction in surface roughness; thus, the program voltage of memory cells can be significantly improved more than 1 V. Simultaneously, the saturation current of n-type metal-oxide-semicondutor field effect transistor (NMOSFET) shifts less than 4%, and cell threshold voltage fluctuations resulting from floating gate coupling are not obviously changed. © 2008 The Japan Society of Applied Physics.