Abstract
We present an automatic layout generation system, called LiB, for the SSI cells used in CMOS VLSI design. LiB takes a transistor-level circuit schematic in SPICE format and outputs a mask layout in CIF. Our layout style is a modification of that proposed by Uehara and van Cleemput in [1]. An optimal transistor chaining algorithm has been developed to derive a transistor placement with a minimum number of diffusion separations. To meet the cell height constraint, large transistors are folded into multiple columns algorithmically. The whole cell is divided into five routing regions. Two regions are on-the-diffusion-island while the other three are rectilinear-shaped routing channels. We propose a graph theoretic method to select nets (subnets) for routing on-the-diffusion-island. A global routing algorithm has been developed to assign the remaining nets to the three rectilinear channels. For the detailed routing, SILK [2], a simulated evolution router, is employed. LiB can be used as a cell library builder or as a subsystem of a random logic module generator. Users can alternate LiB’s layout via a symbolic editor. © 1991 IEEE