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Low EOT and oxide traps for p-substrate Ge MOS device with hafnium nitride interfacial layer
期刊文章

Low EOT and oxide traps for p-substrate Ge MOS device with hafnium nitride interfacial layer

Dun-Bao Ruan, Kuei-Shu Chang-Liao, Wen-Yen Hsu, Shih-Han YiYao-Jen Lee
Vacuum, 卷.179, 109479
09/2020

摘要

Equivalent oxide thickness Ge MOS device Hafnium nitride Interfacial layer Oxide traps Instrumentation Condensed Matter Physics Surfaces Coatings and Films
Effects of interfacial layer on p-substrate germanium (pGe) metal oxide semiconductor (MOS) device were studied in this work. Although excellent characteristics in n-substrate Ge MOS device were reported, pGe MOS device often suffers a poor interface quality and large gate leakage current, while the equivalent oxide thickness (EOT) is scaled down below 1 nm. A novel hafnium nitride (HfN) interfacial layer (IL) is proposed to replace the traditional germanium dioxide thanks to its good thermal stability. As a result, the pGe MOS device with HfN IL exhibits a low EOT of 0.58 nm, a low leakage current density of 2.4 × 10 −4 A/cm 2 , a lower hysteresis value of 150 mV, a better frequency dispersion, and lower oxide/border traps. Therefore, HfN is a promising IL to achieve high performance pGe MOS device.

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