Abstract
A bit-oriented architecture for the digital finite impulse response (FIR) filter with adaptive coefficients is presented. Instead of using multipliers, the FIR operation is regarded as the summation of a larger number of operands. The architecture utilises two new word-level operand compressors, namely six-to-triple and six-to-double compressors. Both of these two compressors, multiple operands can be merged efficiently without long carry propagation. Using such compressors as the basic building blocks, a FIR filter can be implemented as a fast and regular structure that lends itself to automation. Experiments show that the FIR generator based on the proposed architecture could easily achieve a 44 power reduction as compared to the traditional high-speed transposed form.