Logo image
Low-speed scan testing of charge-sharing faults for CMOS domino circuits
Journal article   Peer reviewed

Low-speed scan testing of charge-sharing faults for CMOS domino circuits

C.H. Cheng, W.B. Jone, S.C. Chang and J.S. Wang
Electronics Letters, Vol.36(20), pp.1684-1685
28/09/2000

Abstract

Domino circuits have been widely used to design high-performance processors. However, domino logic suffers from the problem of charge-sharing, which may degrade the output voltage level or even cause an erroneous output value (charge-sharing fault). It is shown that charge-sharing faults are resistant to scan testing and that a killing error might occur because of the lowspeed testing problem caused by scan testing. The testing error is investigated and a DFT technique to efficiently eliminate this problem is proposed.

Metrics

1 Record Views

Details

Logo image