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Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops
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Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops

Xueqing Li, Sumitha George, Yuhua Liang, Kaisheng Ma, Kai Ni, Ahmedullah Aziz, Sumeet Kumar Gupta, John Sampson, Meng-Fan Chang, Yongpan Liu, …
IEEE Transactions on Electron Devices, 卷.65(6), 頁碼.2670-2674
06/2018

摘要

Ferroelectric FET (FeFET) hysteresis negative capacitance nonvolatile flip-flop nonvolatile latch power gating Electronic Optical and Magnetic Materials Electrical and Electronic Engineering
This brief exploits the fusion of low-power logic and nonvolatile memory inside the emerging ferroelectric FETs (FeFETs) and proposes a new nonvolatile D flip-flop (nvDFF) through the device-circuit co-design. Compared with existing FeFET-based nvDFFs with on-demand control of backup and restore (BR), the area overhead is lowered by half, and the routing cost is reduced with embedded backup control into the supply voltage. Circuit simulations show below 5% energy-delay overhead in the normal mode and femtojoule BR energy. This new nvDFF promises area-and energy-efficient nonvolatile computing for power-gating and energy-harvesting applications.

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