摘要
This work proposes a macromodel for a Schottky-type p-GaN gate GaN HEMT. Dynamic on-resistance (DRDS(on)) and dynamic threshold voltage (DVTH) effects are analyzed and incorporated into the channel current model. To address the highly non-linear and voltage-dependent parasitic capacitances, subcircuit-based models are presented to accurately emulate these behaviors. The proposed macromodel is evaluated under a continuous switching platform for DVTH and DRDS(on) effects; moreover, double pulse test (DPT) results are validated against simulation data. Additionally, the proposed monolithic GaN power IC integrates a 650 V, 120 mΩ E-mode HEMT with a gate driver, Schmitt Trigger (ST) and ESD protection on a CMOS compatible GaN-on-Si platform. This design effectively minimizes common source inductance (CSI) and enables a sub-3 ns turn-on time under 400 V / 6 A conditions in a DPT test. Furthermore, the GaN Power IC was evaluated in a 400 W hard-switching boost converter, achieving a peak efficiency of 97.9%.