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Memory-Logic Hybrid Gate with 3-D Stackable Complementary Latches
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Memory-Logic Hybrid Gate with 3-D Stackable Complementary Latches

Chieh Lee, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin 和 Ya-Chin King
IEEE Transactions on Electron Devices, 卷.67(8), 頁碼.3109-3114
08/2020
DOI: https://doi.org/10.1109/TED.2020.3000737

摘要

CMOS logic FinFET memristor ratioed logic resistive random access memory (RRAM) Electronic Optical and Magnetic Materials Electrical and Electronic Engineering
In this article, a single-layer complementary latch (CL) and one multilayer CL which are fully compatible with standard FinFET CMOS processes are characterized and their applications are extensively discussed. Through the complementary pair with the 3-D stackable twin-bit resistive random-access memory (RRAM) which consists of a TaON-based resistive film, the CLs feature great area efficiency and stable output responses. By measurement, the characteristics of the 3-D stackable twin-bit RRAM are discussed. Besides, the power, output voltage distribution, and data restoration time of the CLs are analyzed and compared.

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