Abstract
Effects of in-situ doped (ISD) polycrystalline silicon (poly-Si), which serves as the source, drain and channel, on vertically stacked junctionless (JL) charge-trapping (CT) flash memory devices are investigated for the first time. The vertically stacked JL devices formed by ISD poly-Si channel show minimized program disturb with a large disturb-free window of 4.5 V even when a low program-inhibit voltage (Vinhibit) of 6 V is applied. It can be attributed to the fast programming speed of ISD JL device. Fast programming/erasing (P/E) speeds, good retention and endurance characteristics are also obtained. Therefore, ISD poly-Si is promising for future three-dimensional (3D) CT flash integration.