Abstract
Monolithic 3D integration of high performance MoS 2 and WSe 2 layered semiconductor metal oxide semiconductor field effect transistors (MOSFETs) with electron and hole mobility of 38 and 238 cm 2 were reported. To calculate the circuit area, layouts were designed for single-layer (1 layer) and monolithic 3D (2 layer) CMOS using design rules for the 14 nm technology node. To fabricate the first layer MOSFET, MoS 2 thin flakes are exfoliated on to Si/SiO 2 substrate. Flakes with appropriate thicknesses are etched into rectangular patterns using xenon difluoride followed by source/drain, gate oxide, and metal gate formation. Thick layers of SiO x and ZrO 2 are deposited on top of the bottom layer MoS 2 transistors to reduce the interlayer capacitive coupling between bottom and top layer devices followed by MoS 2 dry transfer and etch. The interlayer capacitance is inversely proportional to the oxide thickness between the top and bottom layer transistors and increasing the oxide thickness decreases the interlayer capacitance. This low-temperature, monolithic 3D integration platform can potentially enable highly integrated and massively interconnected computing platforms with ultralow energy consumption such as neuromorphic computing.