Abstract
In this brief, a bit-serial hybrid VLSI architecture that cosists of both table-look-up and conventional binary modules is proposed to implement FIR digital filters using the residue number system (RNS). The architecture is constructed based on a new theorem for performing the operation a + xβ mod m without look-up tables, where m is a modulus in the RNS, α and β are two numbers in modulo m, and x {0,1}. As compared to a bit-parallel hybrid realization method described recently, the proposed bit-serial one does not need to broadcast input data to the processing elements used and reduces the table-look-up memory in each modulo processor from (B + 2 log 2 A 1 — 1) • B • 2 2B bits to B 2 2B bits, where B is the wordlength of each modulus and N is the number of filter coefficients. As a consequence, it can provide better performance in VLSI implementation for applications where large moduli and/or large filter orders are used. © 1994 IEEE