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On-Chip Jitter Learning for PLL
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On-Chip Jitter Learning for PLL

Wei-Hao ChenShi-Yu Huang
IEEE Design and Test
2021

摘要

Clocks Codes Frequency conversion Jitter Jitter Learning min-MAX TDC Monitoring Online Monitor Peak-to-Peak Jitter Phase locked loops Phase-Locked Loop Watermarking Software Hardware and Architecture Electrical and Electronic Engineering
This work explores one possible active role of an online monitor in the jitter learning process for a Phase-Locked Loop (PLL). For a given PLL producing a high-speed clock signal, its peak-to-peak jitter is often the most important characteristic. An online min-Max Period monitor added at the PLL&null output can be used to assess it on the fly. With such a monitoring feature in place, a feedback loop can be exploited to guide the PLL in a &null process&null which helps decide a proper value of some key operating parameter in the PLL, e.g., the &null level&null affecting the PLL&null loop bandwidth. The results are quite intriguing. Depending on the process status, a proper suppression level can be decided on the fly, and thereby avoiding the worst-case peak-to-peak jitter of the PLL by as much as 21%.

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