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On-Chip Recovery Operation for Self-Aligned Nitride Logic Non-Volatile Memory Cells in High-K Metal Gate CMOS Technology
Journal article   Open access   Peer reviewed

On-Chip Recovery Operation for Self-Aligned Nitride Logic Non-Volatile Memory Cells in High-K Metal Gate CMOS Technology

Po-Yen Lin, Yu-Lun Chiu, Yuh-Te Sung, Jim Chen, Tzong-Sheng Chang, Ya-Chin King and Chrong Jung Lin
IEEE Journal of the Electron Devices Society, Vol.3(6), pp.463-467
01/11/2015

Abstract

Charge pumping nonvolatile memory reliability self-recovery
A new on-chip recovery operation is proposed in the self-aligned nitride (SAN) cell. Merged nitride spacer is sandwiched between high-k metal gate stacks in nano-meter CMOS process. The scaled gate length enables the SAN cell be erased by band-to-band hot hole. For multiple-time-programming operation, two effective recovery methods are proposed to recover on/off window after cycling stress. Both ac and dc methods are applied to eliminate deep-trapped charges via electrical self-heating. Experimental data demonstrates dc recovery methods that provide nearly full damage anneal capability and, in turn, effectively extend SAN cell's endurance level.
url
https://doi.org/10.1109/JEDS.2015.2475257View
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