Abstract
An optimal process integration on the gate insulator (GI) and intrinsic a-Si layer of large-sized amorphous silicon thin film transistor (a-Si TFT) is proposed in this work to effectively reduce off current (Ioff) and threshold voltage (Vth) shift under high and low electrical-field stresses. The proposed optimal integration is to apply the better deposition conditions of gate insulator (GI) and a-Si layer. It is experimentally found that the Ioff of large-sized a-Si TFT with the optimal integration can be reduced by at least 50%, and the Vth shift (ΔVth) after high and low electrical-field stresses can also be reduced by around 40%.