摘要
Electroless etching was used to prepare p- and n-Si nanowire (NW) arrays from Si wafers, with the lengths of the Si NW arrays varied by controlling the etching time. The etching rate was ∼150 nm/min up to 300 min but decreased notably, to 32 nm/min, thereafter. Transmission electron microscopy confirmed that the Si NWs were single-crystalline and aligned along the [001] direction. The dumbbell separation of 0.13 nm, observed using high-resolution high-angle annular-dark field scanning transmission electron microscopy, corresponded to Si atom arrangements projected along the [1-10] zone axis. A statistical study revealed that the average carrier concentrations of the p- and n-Si NW devices were 1.15 × 10 18 and 2.61 × 10 17 cm -3 , respectively, while the average carrier mobilities were 6.66 × 10 -3 and 5.41 × 10 -3 cm 2 V -1 s -1 , respectively. A subsequently prepared p-n Si NW crossed nanojunction exhibited rectifying behavior typical of a p-n junction. Thus the preparation of Si NW arrays from Si wafers through electroless etching appears to be an inexpensive, low-temperature technique for the mass production of various device architectures and applications.