Abstract
Experts have presented a technique that addresses the challenges of developing production-worthy manufacturing processes and ensuring known-good status for individual manufactured devices by providing an accurate and process-insensitive TSV leakage binning capability useful for characterization and test. The first method of the leakage test is the L2VCC method, which converts the leakage current into a voltage by imposing a pull-up device on the TSV node under test. CAF WAS method is the second technique, which has been successfully used for IO pin leakage test with 1-μA LTT. Experts state that the CAF WAS method is superior to the L2VCC method in several aspects, such as in terms of its elegance in using only low-cost logic gates, its ability to detect smaller leakage current, and its ability to perform leakage binning.