Abstract
This paper proposes a new filter bank structure based on the discrete cosine transform (DCT) and inverse DCT (IDCT) using modified autoregressive filter realization for real-time applications. The number of multipliers required in the synthesis bank is only N-1, which is the minimum number of multipliers for the IDCT compared to previous architectures[1,2]. The VLSI implementations of the filter modules show that it can achieve 116Mb/s and 540Mb/s data rate under 2 μm and 0.8 μm CMOS SPDM technology. © 1994 IEEE