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Parameterized all-digital PLL architecture and its compiler to support easy process migration
Journal article   Peer reviewed

Parameterized all-digital PLL architecture and its compiler to support easy process migration

Chao-Wen Tzeng, Shi-Yu Huang and Pei-Ying Chao
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.22(3), pp.621-630
2014

Abstract

Cell-based phase-locked loop (PLL) compiler digital control oscillator (DCO) PLL process resilient
In this paper, we propose a parameterized digitally controlled oscillator that can produce oscillating-clock signal with the tunable frequency covering an entire designated range. Moreover, we formulate the all-digital phase-locked loop optimization process as a search problem, during which we can find a good configuration that not only meets the user-defined requirement but also achieves a smaller area and lower power consumption than a typical manual design. The silicon measurement results show that this is indeed a promising new alternative for analog phase-locked loops, especially for advanced nanometer technologies. © 2013 IEEE.

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