Abstract
This correspondence analyzes the performance of the multistage interconnection networks (MIN's) for interconnecting N processors or N processors to N commonly shared memory modules in a multiprocessor system. A general model, called hierarchical requesting model, has been proposed. The performance of the MIN's with respect to their memory bandwidth is analyzed and is compared to that of a crossbar under the proposed model. Based on the analytical results, we present a task allocation strategy to increase the memory bandwidth of the MIN's. © 1988 IEEE