Logo image
Performance-Driven Channel Pin Assignment Algorithms
期刊文章   同儕審查

Performance-Driven Channel Pin Assignment Algorithms

T. W. Her, T.-C. WangD. F. Wong
IEEE Xplore Digital Library IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 卷.14(7), 頁碼.849-428
1995

摘要

VLSI;circuit layout CAD;computational complexity;delays;integer programming;linear programming;network routing;network topology
In this paper we consider two channel pin assignment problems which take circuit performance into account. The first one is the module implementation selection problem. We are given a net span bound for each critical net and each module has several possible placements of its pins. Our objective is to minimize channel density while satisfying net span constraints. We proved that this problem is NP-complete. For the case when each module has at most 2 pin placements, the problem can be transformed to the 2-SAT problem and hence is polynomial time solvable. We present a heuristic based on this algorithm to solve the general case. The second problem we consider is the module shifting problem. We are given a set of modules whose relative ordering is fixed on each side of the channel but their exact positions are not fixed. We present a polynomial time algorithm to test the feasibility of satisfying the net span constraints by shifting the modules. The algorithm is based on formulating the problem as a special integer linear programming problem which is solvable in polynomial time. We also extend our algorithms to handle multiple channels

相關連結

指標

1 檢視次數

詳細資料

Logo image