摘要
In advanced technologies, on-chip-variation (OCV) has accounted for a large proportion of clock skew, which limits the performance of a circuit. To mitigate the OCV problem, a mesh structure has been widely used in high-performance designs. Unfortunately, clock mesh structure also causes large power consumption and large power-ground surge current. Therefore, recently, several approaches have been proposed to apply resonant clock to reduce power consumption. However, previous works often suffer from area overhead because of the need to insert large decoupling capacitors. In this paper, we propose a novel resonant clock mesh structure, called ping-pong mesh, to overcome these drawbacks. Our ping-pong mesh contains two submeshes, each of which plays the role of the decoupling capacitor of the other, and the clocks in two submeshes operate in completely opposite phases. Our ping-pong mesh has the following two advantages: 1) a ping-pong mesh does not need additional decoupling capacitors as in previous works and 2) a ping-pong mesh can reduce the power-ground surge current about half of previous works. Benchmark data consistently show that our ping-pong mesh does work well in practice.