摘要
A Delay-Locked Loop (DLL) circuit is often useful for the clock synchronization in a chip incorporating multiple functional dies. In this work, we present a process-resilient fault-tolerant DLL design. We will first show that a naove Triple-Module Redundancy (TMR) technique cannot work well unless with a simple yet powerful static timing correction scheme to nullify the adversary effect caused by the voter circuit&null delay. Furthermore, we enhance it with a dynamic scheme so that the overall performance is immune to process variation. Through the proposed schemes, the maximum phase error over 1000 clock cycles between the DLL&null input and output clock signals after locking, which is often considered as the most important performance metric, can be reduced tremendously from 130ps using only naove TMR to 20ps using static timing correction, and then further down to 11ps using the dynamic timing correction.