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Reduced Asymmetric Memory Window between Si-Based n- and p-FeFETs with Scaled Ferroelectric HfZrOx and AlON Interfacial Layer
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Reduced Asymmetric Memory Window between Si-Based n- and p-FeFETs with Scaled Ferroelectric HfZrOx and AlON Interfacial Layer

Hao-Kai Peng, Tien-Hong Kao, Yu-Cheng Kao, Pin-Jiun WuYung-Hsien Wu
IEEE Electron Device Letters
2021

摘要

FeFETs ferroelectric HfZrOx High-k dielectric materials Iron Logic gates memory window non-volatile memory p-FeFET pulsed ID-VG reliability Silicon Substrates Tin Electronic Optical and Magnetic Materials Electrical and Electronic Engineering
The Si-based n- and p-FeFET with 5-nm ferroelectric (FE) HfZrOx (HZO) and high-k AlON interfacial layer (IL) were fabricated for the comparison of memory characteristics and reliability. The memory window (MW) of 1.37 V and 1.25 V are obtained by the n-and p-FeFET respectively by applying pulses of &null V/50 &null The typical MW asymmetry for both types of FeFETs is significantly reduced which is attributed to the reduced remanent polarization (Pr) from the highly scaled HZO and the enhanced voltage drop across the HZO as well as the improved interfacial quality from the AlON IL. In addition, the p-FeFET demonstrates a MW of 1.02 V up to 105 cycles with a long pulse 10-4 s, superior to that of the n-FeFET due to the mitigated hot-electrons induced hole generation. Furthermore, the p-FeFET shows comparable retention performance with the n-FeFET. These results indicate that the p-FeFET possesses the competence of future memory applications without adding process complexity and introducing new substrate material.

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