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Reducing cache conflicts by multi-level cache partitioning and array elements mapping
Journal article   Peer reviewed

Reducing cache conflicts by multi-level cache partitioning and array elements mapping

C.-Y. Chang, J.-P. Sheu and H.-C. Chen
Journal of Supercomputing, Vol.22(2), pp.197-219
06/2002

Abstract

Array padding Cache conflict Cache partitioning Direct mapping Loop tiling Multi-level cache
This article presents an algorithm to reduce cache conflicts and improve cache localities. The proposed algorithm analyzes locality reference space for each reference pattern, partitions the multi-level cache into several parts with different sizes, and then maps array data onto the scheduled cache positions to eliminate cache conflicts. A greedy method for rearranging array variables in declared statement is also developed, to reduce the memory overhead for mapping arrays onto a partitioned cache. Besides, loop tiling and the proposed schemes are combined to exploit opportunities for both temporal and spatial reuse. Atom is used as a tool to develop a simulation of the behavior of the direct-mapping cache to demonstrate that our approach is effective at reducing number of cache conflicts and exploiting cache localities. Experimental results reveal that applying the cache partitioning scheme can greatly reduce the cache conflicts and thus save program execution time in both single-level cache and multi-level cache hierarchies.

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