Abstract
Roughness effect on uniformity and reliability of sequential lateral solidified low-temperature polycrystalline silicon thin-film transistors were studied by comparison of transistors made on a thin-film substrate with and without planarization process. The two-step planarization process, including the wet etching of the precursor and a fine-tuned laser annealing procedure, can reduce the average roughness level to less than 1.4 nm. The results show that transistors without protrusion around the grain boundaries have higher threshold voltage uniformity, smaller subthreshold swing, larger breakdown voltage, and better reliability under high field stress than those made without planarization process. © 2006 The Electrochemical Society.