摘要
Nanoelectronics of two-dimensional (2D) materials and related applications are hindered with critical contact issues with the semiconducting monolayers. To solve these issues, a fundamental challenge is selective and controllable fabrication of p-type or ambipolar transistors with a low Schottky barrier. Most p-type transistors are demonstrated with tungsten selenides (WSe ) but a high growth temperature is required. Here, we utilize seeding promoter and low pressure CVD process to enhance sequential WSe growth with a reduced growth temperature of 800 °C for reduced compositional fluctuations and high hetero-interface quality. Growth behavior of the sequential WSe growth at the edge of patterned graphene is discussed. With optimized growth conditions, high-quality interface of the laterally stitched WSe -graphene is achieved and characterized with transmission electron microscopy (TEM). Device fabrication and electronic performances of the laterally stitched WSe -graphene are presented.