Self-matching SRAM with embedded OTP cells in nanoscale logic CMOS technologies

Sheng-Yen Chien; Po-Yen Lin; Hung-Yu Chen; Chrong-Jung Lin; Ya-Chin King

doi:10.1109/TED.2014.2357585

Self-matching SRAM with embedded OTP cells in nanoscale logic CMOS technologies

期刊文章

同儕審查

Self-matching SRAM with embedded OTP cells in nanoscale logic CMOS technologies

Sheng-Yen Chien, Po-Yen Lin, Hung-Yu Chen, Chrong-Jung Lin 和 Ya-Chin King

IEEE Transactions on Electron Devices, 卷.61(11), 頁碼.3731-3736

11/2014

DOI: https://doi.org/10.1109/TED.2014.2357585

摘要

CMOS logic process

high-k metal gate

logic NVM

process variation

static RAM (SRAM)

Electrical and Electronic Engineering

Electronic

Optical and Magnetic Materials

This paper reports a new static RAM (SRAM) cell featuring its self-matching characteristic for enhanced static noise margin (SNM) in low-voltage applications. This new SRAM employs trimming devices replacing pull-down transistors to compensate mismatches. Through a blanket trimming operation enabling self-matching of the two branches, effective suppression of variability with improved SNM distribution has been successfully demonstrated in nanoscaled SRAMs.

指標

1 檢視次數

詳細資料

題名: Self-matching SRAM with embedded OTP cells in nanoscale logic CMOS technologies
翻譯題名: Self-matching SRAM with embedded OTP cells in nanoscale logic CMOS technologies
創作者：: Sheng-Yen Chien (作者) - National Tsing Hua University
Po-Yen Lin (作者) - Institute of Electronics Engineering, National Tsing Hua University
Hung-Yu Chen (作者) - Institute of Electronics Engineering, National Tsing Hua University
Chrong-Jung Lin (作者) - National Tsing Hua University
Ya-Chin King (作者) - Institute of Electronics Engineering, National Tsing Hua University
學術資源類型: 期刊文章
出版日期: 11/2014
出版資訊: IEEE Transactions on Electron Devices, 卷.61(11), 頁碼.3731-3736
語言: 英語

Self-matching SRAM with embedded OTP cells in nanoscale logic CMOS technologies

摘要

相關連結

指標

詳細資料

National Tsing Hua University 社交媒體