Self-matching SRAM with embedded OTP cells in nanoscale logic CMOS technologies

Sheng-Yen Chien; Po-Yen Lin; Hung-Yu Chen; Chrong-Jung Lin; Ya-Chin King

doi:10.1109/TED.2014.2357585

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Self-matching SRAM with embedded OTP cells in nanoscale logic CMOS technologies

Journal article

Peer reviewed

Self-matching SRAM with embedded OTP cells in nanoscale logic CMOS technologies

Sheng-Yen Chien, Po-Yen Lin, Hung-Yu Chen, Chrong-Jung Lin and Ya-Chin King

IEEE Transactions on Electron Devices, Vol.61(11), pp.3731-3736

01/11/2014

DOI: https://doi.org/10.1109/TED.2014.2357585

Abstract

CMOS logic process

high-k metal gate

logic NVM

process variation

static RAM (SRAM)

This paper reports a new static RAM (SRAM) cell featuring its self-matching characteristic for enhanced static noise margin (SNM) in low-voltage applications. This new SRAM employs trimming devices replacing pull-down transistors to compensate mismatches. Through a blanket trimming operation enabling self-matching of the two branches, effective suppression of variability with improved SNM distribution has been successfully demonstrated in nanoscaled SRAMs. © 2014 IEEE.

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Title: Self-matching SRAM with embedded OTP cells in nanoscale logic CMOS technologies
Creators - without role: Sheng-Yen Chien - National Tsing Hua University
Po-Yen Lin - Institute of Electronics Engineering, National Tsing Hua University
Hung-Yu Chen - Institute of Electronics Engineering, National Tsing Hua University
Chrong-Jung Lin - National Tsing Hua University
Ya-Chin King - Institute of Electronics Engineering, National Tsing Hua University
Publication Details: IEEE Transactions on Electron Devices, Vol.61(11), pp.3731-3736
Identifiers: 9957775037906774
Academic Unit: Institute of Electronics Engineering, College of Electrical Engineering and Computer Science, National Tsing Hua University
Language: English
Resource Type: Journal article

Self-matching SRAM with embedded OTP cells in nanoscale logic CMOS technologies

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