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Semimetal Bi/MoS2 Memristor Exhibiting Ultrahigh Switching Ratio and Mechanistic Insights into Transport via Low-Temperature Characterization
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Semimetal Bi/MoS2 Memristor Exhibiting Ultrahigh Switching Ratio and Mechanistic Insights into Transport via Low-Temperature Characterization

K.-S. Li, M.-K. Huang, H.-M. Chen, W.-F. Wu, Y.-H. Wang, Y.-C. Tseng 和 C.-J. Su
IEEE Transactions on Electron Devices, 卷.73(7), 頁碼.4448-4455
2026
Web of Science ID: WOS:001786146100001

摘要

2-D memristor bismuth cryogenic operation MoS<sub>2</sub> resistive switching (RS) silicon-compatible process sulfur vacancies time-dependent dielectric breakdown (TDDB) reliability wafer-scale integration Bismuth compounds Dielectric materials Electric breakdown Low temperature operations Molybdenum compounds Reliability Schottky barrier diodes Silicon compounds Silicon wafers Sulfur Sulfur compounds Temperature Vacancies WSI circuits 2-D memristor Compatible process Cryogenic operations Memristor Resistive switching Silicon-compatible process Sulfur vacancies Time-dependent dielectric breakdown Time-dependent dielectric breakdown reliability Wafer-scale integration Bismuth Memristors
We report Bi/MoS2/poly-Si memristors fabricated through a CMOS-compatible, transfer-free, and wafer-scale process. The semimetal Bi top electrode (TE) provides a low Schottky barrier and reduced contact resistance, enabling an ultrahigh on/off ratio exceeding 106 , endurance up to 103 cycles, and retention longer than 104 s. The devices show highly uniform bipolar switching with forming-free operation and tight cycle-to-cycle and device-to-device distributions. Time-dependent dielectric breakdown (TDDB) suggests improved resistance to constant-stress degradation in Bi-based devices compared with Al-capped counterparts, which is attributed to suppressed sulfur-vacancy-assisted leakage. Temperature-dependent I-V characteristics down to 20 K reveal distinct conduction regimes: direct tunneling and Poole-Frenkel emission in the high-resistance state (HRS), and a Schottky-to-Ohmic transition in the low-resistance state (LRS). The reduced trap density and contact barrier at the Bi/MoS2 interface account for the high switching ratio and stable low-temperature operation. These findings establish a quantitative correlation between electrode/interface engineering and charge-transport mechanisms, providing mechanistic insights into semimetal-2-D interfaces for low-power and reliable memory applications. © 1963-2012 IEEE.

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