摘要
The SiO 2 tunneling and Si 3 N 4 /HfO 2 trapping layers formed with low temperature (LT) processes on operation characteristics of gate-all-around (GAA) junctionless (JL) charge trapping (CT) flash memory devices were studied in this work. The devices with an Ω-nanowire configuration were also compared. The faster operation speeds and larger memory windows are achieved by a GAA configuration. However, the worse retention characteristics for GAA devices may be caused by the SiO 2 and Si 3 N 4 layer with worse step coverage, which are formed by the LT processes. The coverage issues of dielectrics deposited with LT processes in GAA JL CT flash devices need solutions for 3D memory applications.