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Sleep transistor sizing for leakage power minimization considering temporal correlation
Journal article   Peer reviewed

Sleep transistor sizing for leakage power minimization considering temporal correlation

De-Shiuan Chiou, Yu-Ting Chen, Da-Cheng Juan and Shih-Chieh Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.29(8), pp.1285-1290
08/2010

Abstract

Circuit modeling circuit optimization circuit reliability design automation
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among maximum instantaneous current, IR-drops and sleep transistor networks from a temporal viewpoint. Based on this relationship, we propose an algorithm to reduce the total sizes of sleep transistors in distributed sleep transistor network designs with the consideration of decoupling capacitances is taken. Our method achieves significantly better results than previous works on sleep transistor sizes. © 2010 IEEE.

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