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Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact
Journal article   Peer reviewed

Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

Chan-Yen Chou, Tuan-Yu Hung, Shin-Yueh Yang, Ming-Chih Yew, Wen-Kun Yang and Kuo-Ning Chiang
Microelectronics Reliability, Vol.48(8-9), pp.1149-1154
08/2008

Abstract

Accompanying the popularization of portable and handheld products, high reliability under board level drop test is a great concern to semiconductor manufacturers. In this study, a stress-buffer-enhanced package with fan-out capability is proposed to meet the high requirement of drop test performance. Both drop test experiment and numerical simulation were performed. The results showed the first failure of proposed package passed over 100 drops (mean-life-to-failure over 240 drops). Moreover, the failure of broken trace metal in the stress-buffer-enhanced package which is different from the solder joint failure in the conventional wafer level package was observed both in experiments and dynamic simulations. Simulation results were validated with experimental data and explained how the proposed stress-buffer-enhanced package improved drop test performance. © 2008 Elsevier Ltd. All rights reserved.

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